VLSI Projects

S.NO	PROJECT TITLE
1.	Multi-operand  Redundant Adders On FPGAs
2.	Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
3.	Design of VGA display System Based on FPGA and SRAM
4.	Design and implementation of truncated multipliers   for precision improvement
5.	Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
6.	Analysis of Static Noise Margin and Power Dissipation of a Proposed Low Voltage Swing 8T SRAM cell
7.	Design of Locally-Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools
8.	Novel High Speed Vedic Mathematics Multiplier using Compressors
9.	Implementation and Comparison of Effective Area Efficient Architectures for CSLA
10.	Design of High Performance 64 bit MAC Unit
11.	Enhanced Area Efficient Architecture for 128 bit Modified CSLA
12.	Used self-controllable Voltage Level technique to reduce leakage current in DRAM 4×4 in VLSI
13.	Implementation of Radix 4 Booth Multiplier using MGDI technique
14.	Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology
15.	Design Low Power 10T Full Adder Using Process and Circuit Techniques
16.	Modelling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology
17.	DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM cell for High Speed CMOS Circuits
18.	Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology
19.	FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter
20.	The Design of High Speed UART
21.	A novel fault detection and correction technique for memory applications
22.	Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
23.	Reduction of Leakage Current and Power in Full Sub tractor Using MTCMOS Technique
24.	Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop
25.	Performance Analysis of a New CMOS Output Buffer
26.	A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction
27.	A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
28.	Novel Transistor Level Realization of Ultra Low Power High-speed Adiabatic Vedic Multiplier
29.	Design of Low Power TPG Using LP-LFSR
30.	Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
31.	High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
32.	RTL Design and VLSI Implementation of an efficient Convolution Encoder and Adaptive Viterbi Decoder
33.	Asynchronous Design of Energy Efficient Full Adder
34.	High Speed IEEE-754 Double Precision Floating Point arithmetic unit Using HDL
35.	Design a DSP Operations using Vedic Mathematics
36.	High Performance and Power Efficient 8-bit Carry Select Adder using Hybrid PTL/CMOS Logic Style
37.	Low Power VLSI Circuit Design with Efficient HDL Coding
38.	VLSI Implementation Of A High Speed Single Precision Floating Point multiplier Using verilog
39.	Speed optimization of a FPGA based modified Viterbi Decoder
40.	Accumulator Based 3-Weight Pattern Generation
41.	Real Time Hardware Co-simulation of Edge Detection for Video Processing System
42.	VLSI Based Robust Router Architecture
43.	FPGA Implementation of Secret Communication with VHDL
44.	Design of high speed hybrid carry select adder
45.	A Novel High-Performance CMOS 1 Bit Full-Adder Cell
46.	Design Low Power 10T Full Adder Using Process and Circuit Techniques
47.	High speed Modified Booth Encoder multiplier for signed and unsigned numbers.
48.	Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
49.	Radix-10 Parallel Decimal Multiplier
50.	FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture
51.	BPSK System on Spartan 3E FPGA
52.	Low-power and Area Efficient Carry Select Adder
53.	Hardware Software co-simulation for Image Processing Applications
54.	A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
55.	A New Reversible Design of BCD Adder
56.	Verification Of Four Port Router For Network On Chip
57.	Design and Simulation of UART Serial Communication Module Based on VHDL
58.	High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
59.	Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL
60.	Design and Characterization of Parallel Prefix Adders using FPGAs
61.	Area Optimized Low Power Arithmetic And Logic Unit
62.	Simulation and Implementation of a BPSK Modulator on FPGA
63.	Low-Power and Area-Efficient Carry Select Adder
64.	An Efficient Implementation of Floating Point Multiplier
65.	FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers
66.	Dual Stack Method: A Novel Approach to Low  Leakage and Speed Power Product VLSI Design
67.	A Review on Power optimization of Linear Feedback Shift Register (LFSR) for Low Power Built In Self Test (BIST)
68.	Vending Machine using Verilog
69.	Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units
70.	Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications
71.	LUT Optimization for Memory-Based Computation
72.	Energy-Efficient Design Methodologies High-Performance VLSI Adders
73.	High Performance Full Adder Cell A Comparative Analysis
74.	Implementation of Adder-Subtracter Design with Verilog HDL
75.	Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
76.	Design Of Low Power And High Speed Configurable Booth Multiplier
77.	Design of Automatic Washing Machine Based on Verilog HDL Language
78.	FPGA Design of a Fast 32-bit Floating Point Multiplier Unit
79.	Adiabatic Technique for Energy Efficient Logic Circuits Design
80.	Design and Implementation of Carry Select   Adder without Using Multiplexers
81.	Implementation of Power Efficient Vedic Multiplier
82.	Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops